This invention relates to a circuit for protecting a device or electronic components from an electrostatic static discharge or other source of potentially damaging overvoltage.
Various circuit designs are currently used to protect sensitive components from an electrostatic discharge (ESD). Such circuits are commonly called “ESD clamps” because they act to clamp the sensitive node of a component to ground or other safe voltage when an ESD event occurs. However, each of the conventional ESD clamp designs suffers from one or more problems. Some of the conventional ESD clamp designs and their drawbacks will now be described with reference to FIG. 1, which illustrates three different conventional ESD clamping techniques.
FIG. 1a shows a common type of ESD clamp configured to protect point 101 in the circuit shown. Typically, point 101 is the power rail of an integrated circuit. When a DC voltage is applied to the power rail the ESD clamp is disabled. If power rail 101 is at 0V DC and a signal having a fast rise time (such as an ESD event) is applied to power rail 101, the circuit will clamp the power rail to ground rail 102. Therefore this type of clamp only works when the circuit is not powered.
Point 108 in the circuit is coupled to ground by capacitor 107 and is connected to point 101 by resistor 106 (an RC filter arrangement). When an ESD event occurs at point 101, the voltage at that point increases rapidly. Node 108 does not respond to the ESD event and the input of the inverting amplifier comprising transistors 104 and 105 appears low and its output is driven high. This ensures that the large transistor 103 (typically called the “BIGFET” when it is a large MOSFET) is on to short the charge to ground 102.
In contrast, during normal operation when a DC voltage is applied to the power rail BIGFET 103 is off. BIGFET 103 is turned off because under DC conditions the voltage at point 108 will be the same as the voltage at point 101, causing the input of the inverting amplifier (104 and 105) to be high and therefore the output of the inverting amplifier to be low. The clamp reliably operates only when the initial voltage at 101 is zero and a fast voltage ramp is applied at 101. The protection provided by the clamp of FIG. 1a is therefore disabled during normal operation of the device or components which the clamp is configured to protect.
Furthermore, due to its high capacitance and the possibility of the clamp partially turning on as a result of the fluctuating voltage, the clamp may degrade an AC signal carried at point 101. This kind of clamp is therefore only suitable for protecting those points on a circuit that carry DC or low frequency signals, such as power supply rails. The clamp is unsuitable to protect the pins of an integrated circuit that carry high frequency AC signals, such as the output pins of a radio frequency chip. Finally, the clamp requires a large silicon area in order to accommodate the RC filter (components 106 and 107 of FIG. 1a).
FIG. 1b shows an ESD clamp which uses diodes 112 and 113 configured to shunt an ESD event which occurs at point 101 onto power supply rail 110 or ground 102, depending on its polarity. Point 101 is shown as an input/output port of circuit 114 but could be any point in a circuit requiring protection from ESD events. This type of clamp also requires an ESD clamp of any suitable type across the power supply to conduct positive ESD pulses that are applied between point 101 and ground, and to conduct negative pulses that are applied between point 101 and supply rail 110. In FIG. 1b a BIGFET clamp is shown across the power supply.
An ESD clamp of the type illustrated in FIG. 1b is typically used for protecting a terminal to which AC signals are applied. During normal operation the power rail is held high so a voltage waveform whose voltage does not exceed the rail voltage can be applied to 101 without forward biasing the diodes. No current will flow in the diodes, so there will be no disruption to circuit performance. During an ESD event, current will flow through the diode onto the power rails. The power rails are clamped by a power supply clamp, such as a BIGFET clamp shown in FIG. 1a. 
The ESD protection circuit illustrated in FIG. 1b can not tolerate voltages at point 101 that significantly exceed the supply rail voltage without conducting current through the diodes. If this occurs, the impedance at point 101 is affected and the circuit operation will degrade.
FIG. 1c shows a Grounded Gate NMOS (ggNMOS) 109, which may be used as an ESD clamp between point 101 and ground (GRD) 102. This type of ESD clamp is operational when point 101 is both powered and when it is not powered (i.e. the circuit to be protected is on or off) and is typically used to protect either chip terminals or power rails. A ggNMOS is able to protect nodes that carry AC signals since its triggering mechanism is immune to all but the highest frequency AC signals. However, a ggNMOS does present significant capacitive load for RF signals. The ggNMOS makes use of the parasitic components that are created due to the way that MOS devices are fabricated on CMOS integrated circuits. In practice the ggNMOS can be an NMOS or a PMOS device.
However, a ggNMOS is unsuitable for use in the latest deep sub-micron processes due to the high trigger voltages and hold voltages of the clamp. ggNMOS devices therefore offer limited protection in modern integrated circuits.
The clamp types described above are useful for protecting circuits within chips when they have not yet been soldered down on to a PCB to create a final product such as a mobile phone. Once the chip has been incorporated with other components in to a final product, the final product must be able to tolerate ESD events regardless of whether it is powered or not and the amount of ESD that the circuit must be able to tolerate is significantly higher than the ESD tolerance of a typical chip.
There are three techniques currently used to provide protection to in-situ circuits against system-level ESD events.
(i) Mechanical.
Sensitive nodes in the circuit may be physically isolated from the ESD by housing parts, barriers, plastic packaging etc. However, this is not useful for connections that must be available to the outside world, such as connectors and antennas.
(ii) External Clamps.
Sensitive nodes in a circuit can be electrically isolated/protected using discrete components external to the circuit. However, this is not useful if the circuit will not tolerate external the parasitic load of these external components, such as RF antennas. Furthermore, the use of such components is expensive, in terms of cost, production effort and PCB area.
(iii) Internal Clamps.
Sensitive nodes can be protected to some extent by a circuit shown in FIG. 1b. However, since the BIGFET clamp between the power rails is not effective when the device is powered, the rails must be clamped using other techniques.
The above techniques can provide varying forms of ESD protection, depending on the type of circuit which is to be protected and the circuit technologies involved. However, these techniques do not work very well, especially with high frequency chips fabricated using the latest technologies. As a result, expert PCB and package design has become a critical part of ESD protection.
There are problems with all of the clamp designs currently employed to handle ESD events in an electronic device. There is therefore a need for an improved circuit for protecting an electronic device (such as an integrated circuit) sensitive to ESD events. In particular, there is a need for a circuit capable of protecting an electronic device when that device is both powered and not powered, and additionally capable of protecting points in a device carrying high frequency signals.